Examples

This page contains various generator examples with detailed instructions.

• CMOS logic family
  • Install and launch
  • Supported logic gate types
  • Schematic templates
• CMOS SERDES
  • Structure
  • Setup (for BWRC users)
  • Serializer Generation
    • (Optional) Generate 3-stage SER for higher serialization ratio of M x 2N
  • Deserializer Generation
• CMOS 2:1-mux-based serializer
  • Install and launch
  • Parameterizations
• TISAR ADC
  • Overview
  • Installation
  • Setting up parameters
  • TISARADC architecture
  • SubADC frontend layout generation
  • SubADC backend layout generation
  • SubADC switch generation
  • SubADC top generation
  • SubADC testbench
  • Array generation
  • Clocking path generation
  • Retimer
  • TISARADC body (clock+sar+retimer)
  • Bias
  • Top
  • Full stack generation
  • Contributors